1. Field of the Invention
The present invention relates to semiconductor devices, and in particular, to a capacitor and method of fabricating such capacitor by a damascene process using a pedestal within a trench to increase the surface area of the resultant capacitor.
2. Description of Related Art
In semiconductor fabrication processes, layers of insulating, conducting and semiconducting materials are commonly deposited and patterned to form integrated circuits (IC). Contact vias, i.e., openings, are also commonly formed in insulating materials known as interlevel dielectrics (ILDs). These vias may then be filled with conductive material to interconnect electrical devices and wiring at various levels.
Damascene processing similarly involves etching trenches in insulating layers in a desired pattern for a wiring layer. These trenches are then filled with conductive material to fill the damascene regions thereby producing integrated wires within the damascene regions. Further, in those ICs where contact vias also extend downwardly from the bottom of the trenches, the downwardly extending vias may be simultaneously filled with conductive material. This process is known as dual damascene processing of the IC.
Recent semiconductor device manufacturing technology uses copper (Cu) as a wiring material in semiconductor devices having small feature sizes because copper has low resistivity and high resistance to electro-migration. However, copper's complicated chemical reactions makes copper difficult to pattern and use for metal wiring. For example, copper wiring patterns are easily oxidized when exposed to air. Such oxidation increases the resistance of the wiring pattern. Thus, to prevent oxidation, damascene wiring is frequently used for copper interconnection technology in which trenches are formed in an insulating layer and filled with copper to form conductive lines. Chemical mechanical polishing, or an etch-back process, then planarizes the conductive layer to expose the insulative layer. As a result, a damascene metal wiring pattern remains in the damascene regions.
In these conventional damascene and dual damascene processing techniques, only lateral and/or sidewall areas of the metal wiring patterns in such damascene regions contribute to the areal capacitance of a resultant capacitor formed using such patterns. For instance, U.S. Pat. No. 6,320,244 entitled “Integrated circuit device having dual damascene capacitor” discloses multi-component high-k dielectric films along with a damascene fabricated top electrode whereby only sidewalls of the damascene metal wiring area is used to increase the areal capacitance of the capacitor. U.S. Pat. No. 6,075,691 entitled “Thin film capacitors and process for making them” discloses using the lateral area to increase the areal capacitance of the capacitor.
However, as semiconductor devices continue to decrease in size, increased surface areas within the damascene regions will be needed to provide these modern semiconductors with required high capacitance. Accordingly, a need continues to exist in the art for providing convenient damascene processing techniques to enable improved high-k dielectric capacitors.